`include "/home/lab/lab14/Computer_architecture/homwork/mux16_4to1/src/mux16_4to1.v"
`timescale 1ns/1ns
module tb_mux16_4to1; reg [15:0]D_IN0, D_IN1, D_IN2, D_IN3; reg [1:0]SEL; wire [15:0]D_OUT; mux16_4to1 mux16_4to1_inst(.D_IN0(D_IN0), .D_IN1(D_IN1), .D_IN2(D_IN2), .D_IN3(D_IN3), .SEL(SEL), .D_OUT(D_OUT));
    initial
    begin
        $display("start a clock pulse");
        $dumpfile("tb_mux16_4to1.vcd");
        $dumpvars(1,tb_mux16_4to1);
    end
    bit [1:0] i;//in systemverilog, we can use the bit [1:0] instead to interger 
    initial begin
        SEL = 2'b00;D_IN0 = 16'h0;D_IN1 = 16'h0;D_IN2 = 16'h0;D_IN3 = 16'h0;
        //Start to Simulation
        /*
        SEL = 2'b00;D_IN0 = 16'hABCD;D_IN1 = 16'hACBD;D_IN2 = 16'hBCDA;D_IN3 = 16'hBDAC;
        #1
        SEL = 2'b01;D_IN0 = 16'hABCD;D_IN1 = 16'hACBD;D_IN2 = 16'hBCDA;D_IN3 = 16'hBDAC;
        #1
        SEL = 2'b10;D_IN0 = 16'hABCD;D_IN1 = 16'hACBD;D_IN2 = 16'hBCDA;D_IN3 = 16'hBDAC;
        #1
        SEL = 2'b11;D_IN0 = 16'hABCD;D_IN1 = 16'hACBD;D_IN2 = 16'hBCDA;D_IN3 = 16'hBDAC;
        #1*/
        for ( i= 0; i<5 ;i=i+1 ) begin
            #1
            SEL = i;D_IN0=$random%255;D_IN1=$random %255;D_IN2=$random %255;D_IN3=$random %255;
 
        end
        $stop;
    end
endmodule
